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| rev. 4135f?8051?11/06 1 features ? pin and software compatibility with standard 80c51 products and 80c51fx/rx/rx+ ? plug-in replacement of intel?s 8xc251sx ? c251 core: intel?s mcs ? 251 d-step compliance ? 40-byte register file ? registers accessible as bytes, words or dwords ? three-stage instruction pipeline ? 16-bit internal code fetch ? enriched c51 instruction set ? 16-bit and 32-bit alu ? compare and conditional jump instructions ? expanded set of move instructions ? linear addressing ? 1 kbyte of on-chip ram ? external memory space (code/data) programma ble from 64 kilobytes to 256 kilobytes ? tsc87251g2d: 32 kilobytes of on-chip eprom/otprom ? single pulse programming algorithm ? tsc83251g2d: 32 kilobytes of on-chip masked rom ? tsc80251g2d: romless version ? four 8-bit parallel i/o ports (ports 0, 1, 2 and 3 of the standard 80c51) ? serial i/o port: full duplex uart (80c51 compatible) with independent baud rate generator ? sslc: synchronous serial link controller ? twi multi-master protocol ? wire and spi master and slave protocols ? three 16-bit timers/counters (timers 0, 1 and 2 of the standard 80c51) ? ewc: event and waveform controller ? compatible with intel?s programmable counter array (pca) ? common 16-bit timer/counter reference with four possible clock sources (fosc/4, fosc/12, timer 1 and external input) ? five modules, each with four programmable modes: ? 16-bit software timer/counter ? 16-bit timer/counter capture input and software pulse measurement ? high-speed output and 16-bit software pulse width modulation (pwm) ? 8-bit hardware pwm without overhead ? 16-bit watchdog timer/counter capability ? secure 14-bit hardware watchdog timer ? power management ? power-on reset (integrated on the chip) ? power-off flag (cold and warm resets) ? software programmable system clock ? idle mode ? power-down mode ? keyboard interrupt interface on port 1 ? non maskable interrupt input (nmi) ? real-time wait states inputs (wait#/await#) ? once mode and full speed real-time in-circuit emulation support (third party vendors) ? high speed versions: ? 4.5v to 5.5v ? 16 mhz and 24 mhz ? typical operating current: 35 ma at 24 mhz 24 ma at 16 mhz ? typical power-down current: 2 a ? low voltage version: ? 2.7v to 5.5v ?16 mhz 8/16-bit microcontroller with serial communication interfaces tsc80251g2d tsc83251g2d tsc87251g2d at80251g2d at83251g2d at87251g2d
2 at/tsc8x251g2d 4135f?8051?11/06 ? typical operating current:11 ma at 3v ? typical power-down current: 1 a ? temperature ranges: commercial (0 c to +70 c), industrial (-40 c to +85 c), automotive ((-40c to +85c) rom only) ? option: extended range (-55 c to +125 c) ? packages: pdil 40, plcc 44 and vqfp 44 ? options: known good dice and ceramic packages description the tsc80251g2d products are derivatives of the atmel microcontroller family based on the 8/16-bit c251 architecture. this family of products is tailored to 8/16-bit microcontro ller applications requiring an increased instruction throughput, a reduced operating frequency or a larger addressable memory space. the architecture can provide a significant code size reduction when compiling c programs while fully preserving the legacy of c51 assembly routines. the tsc80251g2d derivatives are pin and software compat ible with standard 80c51/fx/rx/rx+ with extended on-chip data memory (1 kbyte ram) and up to 256 kilobytes of external code and data. additionally, the tsc83251g2d and tsc87251g2d provide on-chip code memory: 32 kilobytes rom and 32 kilobytes eprom/otprom respectively. they provide transparent enhancements to intel?s 8xc251sx family with an additional synchronous serial link controller (sslc supporting twi, wire and spi protocols), a keyboard interrupt interface, a dedicated baud rate generator for uart, and power management features. tsc80251g2d derivatives are optimized for speed and for low power consumption on a wide voltage range. note: 1. this datasheet provides the technical description of the tsc80251g2d derivatives. for further information on the device usage, please request the tsc80251 programmer?s guide and the tsc80251g1d design guide and errata sheet. typical applications ? isdn terminals ? high-speed modems ? pabx (soho) ?line cards ? dvd rom and players ?printers ? plotters ? scanners ? banking machines ? barcode readers ? smart cards readers ? high-end digital monitors ? high-end joysticks ? high-end tv?s 3 at/tsc8x251g2d 4135f?8051?11/06 block diagram 16-bit memory code 16-bit memory address 16-bit instruction bus 24-bit program counter bus 8-bit data bus 24-bit data address bus 8-bit internal bus peripheral interface unit vdd vss vss1 p3(a16) p1(a17) p2(a15-8) p0(ad7-0) rst xtal2 xtal1 nmi ea#/vpp ale/prog# psen# timers 0, 1 and 2 event and waveform controller twi/spi/ m wire controller watchdog timer power management clock unit clock system prescaler keyboard interface bus interface unit cpu ports 0-3 interrupt handler unit ram 1 kbyte rom uart baud rate generator await# eprom otprom 32 kb vss2 4 at/tsc8x251g2d 4135f?8051?11/06 pin description pinout figure 1. tsc80251g2d 40-pin dip package figure 2. tsc80251g2d 44-pin plcc package tsc80251g2d 7 8 9 10 11 12 13 14 16 15 17 18 19 20 1 2 3 4 5 6 34 33 32 31 30 29 28 27 25 26 24 23 22 21 40 39 38 37 36 35 p1.5/cex2/miso p1.6/cex3/scl/sck/wait# p1.7/a17/cex4/sda/mosi/wclk rst p3.0/rxd p3.1/txd p3.2/int0# p3.3/int1# p3.4/t0 p3.5/t1 p1.4/cex1/ss# p1.3/cex0 p1.2/eci p1.1/t2ex p1.0/t2 vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea#/vpp psen# ale/prog# p2.7/a15 p2.6/a14 p2.5/a13 p3.7/a16/rd# xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p3.6/wr# tsc80251g2d p1.4/cex1/ss# p1.3/cex0 p1.2/eci p1.1/t2ex p1.0/t2 vss1 vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p3.7/a16/rd# xtal2 xtal1 vss vss2 p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p3.6/wr# 39 38 37 36 35 34 33 32 29 30 31 7 8 9 10 11 12 13 14 17 16 15 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 44 43 42 41 40 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea#/vpp psen# ale/prog# nmi p2.7/a15 p2.6/a14 p2.5/a13 p1.5/cex2/miso p1.6/cex3/scl/sck/wait# p1.7/a17/cex4/sda/mosi/wclk rst p3.0/rxd await# p3.1/txd p3.2/int0# p3.3/int1# p3.4/t0 p3.5/t1 1 5 at/tsc8x251g2d 4135f?8051?11/06 figure 3. tsc80251g2d 44-pin vqfp package tsc80251g2d p1.4/cex1/ss# p1.3/cex0 p1.2/eci p1.1/t2ex p1.0/t2 vss1 vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p3.7/a16/rd# xtal2 xtal1 vss vss2 p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p3.6/wr# 33 32 31 30 29 28 27 26 23 24 25 1 2 3 4 5 6 7 8 11 10 9 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea#/vpp psen# ale/prog# nmi p2.7/a15 p2.6/a14 p2.5/a13 p1.5/cex2/miso p1.6/cex3/scl/sck/wait# p1.7/a17/cex4/sda/mosi/wclk rst p3.0/rxd await# p3.1/txd p3.2/int0# p3.3/int1# p3.4/t0 p3.5/t1 6 at/tsc8x251g2d 4135f?8051?11/06 table 1. tsc80251g2d pin assignment dip plcc vqfp name dip plcc vqfp name 1 39vss1 23 17vss2 1 2 40 p1.0/t2 21 24 18 p2.0/a8 2 3 41 p1.1/t2ex 22 25 19 p2.1/a9 3 4 42 p1.2/eci 23 26 20 p2.2/a10 4 5 43 p1.3/cex0 24 27 21 p2.3/a11 5 6 44 p1.4/cex1/ss# 25 28 22 p2.4/a12 6 7 1 p1.5/cex2/miso 26 29 23 p2.5/a13 7 8 2 p1.6/cex3/scl/sck/wait# 27 30 24 p2.6/a14 8 9 3 p1.7/a17/cex4/sda/mosi/wclk 28 31 25 p2.7/a15 9 10 4 rst 29 32 26 psen# 10 11 5 p3.0/rxd 30 33 27 ale/prog# 12 6 await# 34 28 nmi 11 13 7 p3.1/txd 31 35 29 ea#/vpp 12 14 8 p3.2/int0# 32 36 30 p0.7/ad7 13 15 9 p3.3/int1# 33 37 31 p0.6/ad6 14 16 10 p3.4/t0 34 38 32 p0.5/ad5 15 17 11 p3.5/t1 35 39 33 p0.4/ad4 16 18 12 p3.6/wr# 36 40 34 p0.3/ad3 17 19 13 p3.7/a16/rd# 37 41 35 p0.2/ad2 18 20 14 xtal2 38 42 36 p0.1/ad1 19 21 15 xtal1 39 43 37 p0.0/ad0 20 22 16 vss 40 44 38 vdd 7 at/tsc8x251g2d 4135f?8051?11/06 signals table 2. product name signal description signal name type description alternate function a17 o 18 th address bit output to memory as 18th exter nal address bit (a17) in extended bus applications, depending on the values of bits rd0 and rd1 in uconfig0 byte (see table 13, page 20). p1.7 a16 o 17 th address bit output to memory as 17th exter nal address bit (a16) in extended bus applications, depending on the values of bits rd0 and rd1 in uconfig0 byte (see table 13, page 20). p3.7 a15:8 (1) o address lines upper address lines fo r the external bus. p2.7:0 ad7:0 (1) i/o address/data lines multiplexed lower address lines and data for the external memory. p0.7:0 ale o address latch enable ale signals the start of an external bus cycle and indicates that valid address information are available on li nes a16/a17 and a7:0. an external latch can use ale to demultiplex the address from address/data bus. ? await# i real-time asynchronous wait states input when this pin is active (low level), the memory cycle is stretched until it becomes high. when using the product name as a pin-for-pin replacement for a 8xc51 product, await# can be unconnected without loss of compatibility or power consumption increase (on-chip pull-up). not available on dip package. ? cex4:0 i/o pca input/output pins cexx are input signals for the pca capture mode and output signals for the pca compare and pwm modes. p1.7:3 ea# i external access enable ea# directs program memory accesses to on-chip or off-chip code memory. for ea# = 0, all program memory accesses are off-chip. for ea# = 1, an access is on-chip rom if the address is within the range of the on-chip rom; otherwise the access is off-chip. the value of ea# is latched at reset. for devices without rom on-chip, ea# must be strapped to ground. ? eci o pca external clock input eci is the external clock input to the 16-bit pca timer. p1.2 miso i/o spi master input slave output line when spi is in master mode, miso receives data from the slave peripheral. when spi is in slave mode, miso outputs data to the master controller. p1.5 mosi i/o spi master output slave input line when spi is in master mode, mosi outputs data to the slave peripheral. when spi is in slave mode, mosi receives data from the master controller. p1.7 int1:0# i external interrupts 0 and 1 int1#/int0# inputs set ie1:0 in the tcon register. if bits it1:0 in the tcon register are set, bits ie1:0 are set by a falling edge on int1#/int0#. if bits it1:0 are cleared, bits ie1:0 are set by a low level on int1#/int0#. p3.3:2 8 at/tsc8x251g2d 4135f?8051?11/06 nmi i non maskable interrupt holding this pin high for 24 oscill ator periods triggers an interrupt. when using the product name as a pi n-for-pin replacement for a 8xc51 product, nmi can be unconnected without loss of compatibility or power consumption increase (on-chip pull-down). not available on dip package. ? p0.0:7 i/o port 0 p0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. to avoid any paraitic current consumption, floating p0 inputs must be polarized to v dd or v ss . ad7:0 p1.0:7 i/o port 1 p1 is an 8-bit bidirectional i/o port with internal pull-ups. p1 provides interrupt capability for a keyboard interface. ? p2.0:7 i/o port 2 p2 is an 8-bit bidirectional i/o port with internal pull-ups. a15:8 p3.0:7 i/o port 3 p3 is an 8-bit bidirectional i/o port with internal pull-ups. ? prog# i programming pulse input the programming pulse is applied to this input for programming the on-chip eprom/otprom. ? psen# o program store enable/read signal output psen# is asserted for a memory address range that depends on bits rd0 and rd1 in uconfig0 byte (see ). ? rd# o read or 17 th address bit (a16) read signal output to external data memory depending on the values of bits rd0 and rd1 in uconfig0 byte (see table 13, page 20). p3.7 rst i reset input to the chip holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage greater than v ih1 is applied, whether or not the oscillator is running. this pin has an internal pull-down re sistor which allows the device to be reset by connecting a capacitor between this pin and vdd. asserting rst when the chip is in idle mode or power-down mode returns the chip to normal operation. ? rxd i/o receive serial data rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2 and 3. p3.0 scl i/o twi serial clock when twi controller is in master mode, scl outputs the serial clock to slave peripherals. when twi controller is in slave mode, scl receives clock from the master controller. p1.6 sck i/o spi serial clock when spi is in master mode, sck outputs clock to the slave peripheral. when spi is in slave mode, sck receives clock from the master controller. p1.6 sda i/o twi serial data sda is the bidirectional twi data line. p1.7 ss# i spi slave select input when in slave mode, ss# enables the slave mode. p1.4 table 2. product name signal description (continued) signal name type description alternate function 9 at/tsc8x251g2d 4135f?8051?11/06 t1:0 i/o timer 1:0 external clock inputs when timer 1:0 operates as a counter, a falling edge on the t1:0 pin increments the count. ? t2 i/o timer 2 clock input/output for the timer 2 capture mode, t2 is the external clock input. for the timer 2 clock-out mode, t2 is the clock output. p1.0 t2ex i timer 2 external input in timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. in auto-reload mode, a falling edge causes the timer 2 register to be reloaded. in the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. p1.1 txd o transmit serial data txd outputs the shift clock in serial i/o mode 0 and transmits data in serial i/o modes 1, 2 and 3. p3.1 vdd pwr digital supply voltage connect this pin to +5v or +3v supply voltage. ? vpp i programming supply voltage the programming supply voltage is app lied to this input for programming the on-chip eprom/otprom. ? vss gnd circuit ground connect this pin to ground. ? vss1 gnd secondary ground 1 this ground is provided to reduc e ground bounce and improve power supply bypassing. connection of this pin to ground is recommended. however, when using the tsc80251g2d as a pin-for-pin replacement for a 8xc51 product, vss1 can be unconnected without loss of compatibility. not available on dip package. ? vss2 gnd secondary ground 2 this ground is provided to reduc e ground bounce and improve power supply bypassing. connection of this pin to ground is recommended. however, when using the tsc80251g2d as a pin-for-pin replacement for a 8xc51 product, vss2 can be unconnected without loss of compatibility. not available on dip package. ? wait# i real-time synchronous wait states input the real-time wait# input is enabled by setting rtwe bit in wcon (s:a7h). during bus cycles, the external memory system can signal ?system ready? to the microcontroller in real time by controlling the wait# input signal. p1.6 wclk o wait clock output the real-time wclk output is enabled by setting rtwce bit in wcon (s:a7h). when enabled, the wclk output produces a square wave signal with a period of one half the oscillator frequency. p1.7 wr# o write write signal output to external memory. p3.6 xtal1 i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. xtal1 is the clock source for internal timing. ? table 2. product name signal description (continued) signal name type description alternate function 10 at/tsc8x251g2d 4135f?8051?11/06 note: the description of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the non-page mode chip con- figuration. if the chip is configured in page mode operation, port 0 carries the lower address bits (a7:0) while port 2 carries the upper address bits (a15:8) and the data (d7:0). xtal2 o output of the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave xtal2 unconnected. ? table 2. product name signal description (continued) signal name type description alternate function 11 at/tsc8x251g2d 4135f?8051?11/06 address spaces the tsc80251g2d derivatives implement four different address spaces: ? on-chip rom program/code memory (not present in romless devices) ? on-chip ram data memory ? special function registers (sfrs) ? configuration array program/code memory the tsc83251g2d and tsc87251g2d implement 32 kb of on-chip program/code memory. figure 4 shows the split of the internal and external program/code memory spaces. if ea# is tied to a high level, the 32-kbyte on-chip program memory is mapped in the lower part of segment ff: where the c251 core jumps after reset. the rest of the program/code memory space is mapped to the external memory. if ea# is tied to a low level, the internal program/code memory is not used and all the accesses are directed to the external memory. the tsc83251g2d products provide the internal program/code memory in a masked rom memory while the tsc87251g2d products provide it in an eprom memory. for the tsc80251g2d products, there is no internal program/code memory and ea# must be tied to a low level. figure 4. program/code memory mapping note: special care should be taken when the program counter (pc) increments: if the program executes exclusively from on-chip code memory (not from external mem- ory), beware of executing code from the upper eight bytes of the on-chip rom (ff:7ff8h-ff:7fffh). because of its pipeline capability, the tsc80251g2d derivative may attempt to prefetch code from external memory (at an address above ff:7fffh) and thereby disrupt i/o ports 0 and 2. fetching code constants from these 8 bytes does not affect ports 0 and 2. when pc reaches the end of segment ff:, it loops to the reset address ff:0000h (for on-chip rom/eprom code memory program/code segments program/code external memory space 32 kb ea# = 0 ea# = 1 32 kb 32 kb reserved 64 kb 128 kb ff:ffffh ff:8000h ff:7fffh ff:0000h fe:ffffh fe:0000h fd:ffffh 01:ffffh 01:0000h 02:0000h 00:ffffh 00:0000h 12 at/tsc8x251g2d 4135f?8051?11/06 compatibility with the c51 architecture). when pc increments beyond the end of seg- ment fe:, it continues at the reset address ff:0000h (linearity). when pc increments beyond the end of segment 01:, it loops to the beginning of segment 00: (this prevents from its going into the reserved area). data memory the tsc80251g2d derivatives implement 1 kbyte of on-chip data ram. figure 5 shows the split of the internal and external data memory spaces. this memory is mapped in the data space just over the 32 bytes of registers area (see tsc80251 pro- grammers? guide). hence, the part of the on-chip ram located from 20h to ffh is bit addressable. this on-chip ram is not accessible through the program/code memory space. for faster computation with the on-chip rom/eprom code of the tsc83251g2d/tsc87251g2d, its upper 16 kb are also mapped in the upper part of the region 00: if the on-chip code memory map configuration bit is cleared (emap# bit in uconfig1 byte, see figure ). however, if ea# is tied to a low level, the tsc80251g2d derivative is running as a romless product and the code is actually fetched in the corresponding external memory (i.e. the upper 16 kb of the lower 32 kb of the segment ff:). if emap# bit is set, the on-chip rom is not accessible through the region 00:. all the accesses to the portion of the data space with no on-chip memory mapped onto are redirected to the external memory. figure 5. data memory mapping on-chip rom/eprom code memory data segments data external memory space 16 kb ea# = 0 ea# = 1 32 kb 32 kb reserved 64 kb a47 kb ff:ffffh ff:8000h ff:7fffh ff:0000h fe:ffffh fe:0000h fd:ffffh 01:ffffh 01:0000h 02:0000h 00:ffffh 00:0420h 32 bytes reg. ram data 1 kbyte 16 kb 00:c000h 00:bfffh emap# = 1 emap# = 0 16 kb 64 kb 13 at/tsc8x251g2d 4135f?8051?11/06 special function registers the special function registers (sfrs) of the tsc80251g2d derivatives fall into the categories detailed in table 1 to table 9. sfrs are placed in a reserved on-chip memory region s: which is not represented in the data memory mapping (figure 5). the relative addresses within s: of these sfrs are provided together with their reset values in table . they are upward compatible with the sfrs of the standard 80c51 and the intel?s 80c251sx family. in this table, the c251 core registers are identified by note 1 and are described in the tsc80251 program- mer?s guide. the other sfrs are described in the tsc80251g1d design guide. all the sfrs are bit-addressable using the c251 instruction set. table 1. c251 core sfrs note: 1. these sfrs can also be accessed by their corresponding registers in the register file. table 2. i/o port sfrs table 3. timers sfrs mnemonic name mnemonic name acc (1) accumulator sph (1) stack pointer high - msb of spx b (1) b register dpl (1) data pointer low byte - lsb of dptr psw program status word dph (1) data pointer high byte - msb of dptr psw1 program status word 1 dpxl (1) data pointer extended low byte of dpx - region number sp (1) stack pointer - lsb of spx mnemonic name mnemonic name p0 port 0 p2 port 2 p1 port 1 p3 port 3 mnemonic name mnemonic name tl0 timer/counter 0 low byte tmod timer/counter 0 and 1 modes th0 timer/counter 0 high byte t2con timer/counter 2 control tl1 timer/counter 1 low byte t2mod timer/counter 2 mode th1 timer/counter 1 high byte rcap2l timer/counter 2 reload/capture low byte tl2 timer/counter 2 low byte rcap2h timer/counter 2 reload/capture high byte th2 timer/counter 2 high byte wdtrst watchdog timer reset tcon timer/counter 0 and 1 control 14 at/tsc8x251g2d 4135f?8051?11/06 table 4. serial i/o port sfrs table 5. sslc sfrs table 6. event waveform control sfrs mnemonic name mnemonic name scon serial control saddr slave address sbuf serial data buffer brl baud rate reload saden slave address mask bdrcon baud rate control mnemonic name mnemonic name sscon synchronous serial control ssadr synchronous serial address ssdat synchronous serial data ssbr synchronous serial bit rate sscs synchronous serial control and status mnemonic name mnemonic name ccon ewc-pca timer/counter control ccap0l ewc-pca compare capture module 0 low register cmod ewc-pca timer/counter mode ccap1l ewc-pca compare capture module 1 low register cl ewc-pca timer/counter low register ccap2l ewc-pca compare capture module 2 low register ch ewc-pca timer/counter high register ccap3l ewc-pca compare capture module 3 low register ccapm0 ewc-pca timer/counter mode 0 ccap4l ewc-pca compare capture module 4 low register ccapm1 ewc-pca timer/counter mode 1 ccap0h ewc-pca compare capture module 0 high register ccapm2 ewc-pca timer/counter mode 2 ccap1h ewc-pca compare capture module 1 high register ccapm3 ewc-pca timer/counter mode 3 ccap2h ewc-pca compare capture module 2 high register ccapm4 ewc-pca timer/counter mode 4 ccap3h ewc-pca compare capture module 3 high register ccap4h ewc-pca compare capture module 4 high register 15 at/tsc8x251g2d 4135f?8051?11/06 table 7. system management sfrs table 8. interrupt sfrs table 9. keyboard interface sfrs mnemonic name mnemonic name pcon power control ckrl clock reload powm power management wcon synchronous real-time wait state control mnemonic name mnemonic name ie0 interrupt enable control 0 ipl0 interrupt priority control low 0 ie1 interrupt enable control 1 iph1 interrupt priority control high 1 iph0 interrupt priority control high 0 i pl1 interrupt priority control low 1 mnemonic name mnemonic name p1ie port 1 input interrupt enable p1ls port 1 level selection p1f port 1 flag 16 at/tsc8x251g2d 4135f?8051?11/06 notes: 1. these registers are described in the tsc80251 programmer?s guide (c251 core registers). 2. in twi and spi modes, sscon is splitted in two separate registers. sscon reset value is 0000 0000 in twi mode and 0000 0100 in spi mode. 3. in read and write modes, sscs is splitted in two separate registers. sscs reset value is 1111 1000 in read mode and 0000 0000 in write mode. table 10. sfr descriptions 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ch 0000 0000 ccap0h 0000 0000 ccap1h 0000 0000 ccap2h 0000 0000 ccap3h 0000 0000 ccap4h 0000 0000 ffh f0h b (1) 0000 0000 f7h e8h cl 0000 0000 ccap0l 0000 0000 ccap1l 0000 0000 ccap2l 0000 0000 ccap3l 0000 0000 ccap4l 0000 0000 efh e0h acc (1) 0000 0000 e7h d8h ccon 00x0 0000 cmod 00xx x000 ccapm0 x000 0000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 dfh d0h psw (1) 0000 0000 psw1 (1) 0000 0000 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 cfh c0h c7h b8h ipl0 x000 0000 saden 0000 0000 sph (1) 0000 0000 bfh b0h p3 1111 1111 ie1 xx0x xxx0 ipl1 xx0x xxx0 iph1 xx0x xxx0 iph0 x000 0000 b7h a8h ie0 0000 0000 saddr 0000 0000 afh a0h p2 1111 1111 wdtrst 1111 1111 wcon xxxx xx00 a7h 98h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 p1ls 0000 0000 p1ie 0000 0000 p1f 0000 0000 9fh 90h p1 1111 1111 ssbr 0000 0000 sscon (2) sscs (3) ssdat 0000 0000 ssadr 0000 0000 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 ckrl 0000 1000 powm 0xxx xxxx 8fh 80h p0 1111 1111 sp (1) 0000 0111 dpl (1) 0000 0000 dph (1) 0000 0000 dpxl (1) 0000 0001 pcon 0000 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f reserved 17 at/tsc8x251g2d 4135f?8051?11/06 configuration bytes the tsc80251g2d derivatives provide user de sign flexibility by configuring certain operating features at device reset. these features fall into the following categories: ? external memory interface (page mode, address bits, programmed wait states and the address range for rd#, wr#, and psen#) ? source mode/binary mode opcodes ? selection of bytes stored on the stack by an interrupt ? mapping of the upper portion of on-chip code memory to region 00: two user configuration bytes uconfig0 (see table 11) and uconfig1 (see table 12) provide the information. when ea# is tied to a low level, the configuration bytes are fetched from the external address space. the tsc80251g2d derivatives reserve the top eight bytes of the mem- ory address space (ff:fff8h-ff:ffffh) for an external 8-byte configuration array. only two bytes are actually used: uconfig0 at ff:fff8h and uconfig1 at ff:fff9h. for the mask rom devices, configuration information is stored in on-chip memory (see rom verifying). when ea# is tied to a high level, the configuration information is retrieved from the on-chip memory instead of the external address space and there is no restriction in the usage of the external memory. 18 at/tsc8x251g2d 4135f?8051?11/06 table 11. configuration byte 0 uconfig0 notes: 1. uconfig0 is fetched twice so it can be properly read both in page or non-page modes. if p2.1 is cleared during the first data fetch, a page mode configuration is used, otherwise the subsequent fetches are performed in non-page mode. 2. this selection provides compatibility with the standard 80c51 hardware which is mul- tiplexing the address lsb and the data on port 0. 76543210 - wsa1# wsa0# xale# rd1 rd0 page# src bit number bit mnemonic description 7- reserved set this bit when writing to uconfig0. 6wsa1# wait state a bits select the number of wait states for rd#, wr# and psen# signals for external memory accesses (all regions except 01:). wsa1# wsa0# number of wait states 00 3 01 2 10 1 11 0 5wsa0# 4xale# extend ale bit clear to extend the duration of the ale pulse from t osc to 3t osc. set to minimize the duration of the ale pulse to 1t osc . 3 rd1 memory signal select bits specify a 18-bit, 17-bit or 16-bit exte rnal address bus and the usage of rd#, wr# and psen# signals (see table 13). 2 rd0 1page# page mode select bit (1) clear to select the faster page mode with a15:8/d7:0 on port 2 and a7:0 on port 0. set to select the non-page mode (2) with a15:8 on port 2 and a7:0/d7:0 on port 0. 0src source mode/binary mode select bit clear to select the binary mode. set to select the source mode. 19 at/tsc8x251g2d 4135f?8051?11/06 table 12. configuration byte 1 uconfig1 notes: 1. the csize is only available on eprom/otprom products. 2. two or four bytes are transparently popped according to intr when using the reti instruction. intr must be set if interrupts are used with code executing outside region ff:. 3. use only for step a compatibility; set this bit when wsb1:0# are used. 76543210 csize - - intr wsb wsb1# wsb0# emap# bit number bit mnemonic description 7 csize tsc87251g2d on-chip code memory size bit (1) clear to select 16 kb of on-chip code memory (tsc87251g1d product). set to select 32 kb of on-chip code memory (tsc87251g2d product). tsc80251g2d tsc83251g2d reserved set this bit when writing to uconfig1. 6- reserved set this bit when writing to uconfig1. 5- reserved set this bit when writing to uconfig1. 4intr interrupt mode bit (2) clear so that the interrupts push two bytes onto the stack (the two lower bytes of the pc register). set so that the interrupts push four bytes onto the stack (the three bytes of the pc register and the psw1 register). 3wsb wait state b bit (3) clear to generate one wait state for memory region 01:. set for no wait states for memory region 01:. 2wsb1# wait state b bits select the number of wait states for rd#, wr# and psen# signals for external memory accesses (only region 01:). wsb1# wsb0# number of wait states 00 3 01 2 10 1 11 0 1wsb0# 0emap# on-chip code memory map bit clear to map the upper 16 kb of on-chip code memory (at ff:4000h- ff:7fffh) to the data space (at 00:c000h-00:ffffh). set not to map the upper 16 kb of on-chip code memory (at ff:4000h- ff:7fffh) to the data space. 20 at/tsc8x251g2d 4135f?8051?11/06 configuration byte 1 table 13. address ranges and usage of rd#, wr# and psen# signals notes: 1. this selection provides compatibility with the standard 80c51 hardware which has separate external memory spaces for data and code. rd1 rd0 p1.7 p3.7/rd# psen# wr# external memory 00a17a16 read signal for all external memory locations write signal for all external memory locations 256 kb 0 1 i/o pin a16 read signal for all external memory locations write signal for all external memory locations 128 kb 1 0 i/o pin i/o pin read signal for all external memory locations write signal for all external memory locations 64 kb 1 1 i/o pin read signal for regions 00: and 01: read signal for regions fe: and ff: write signal for all external memory locations 2 64 kb (1) 21 at/tsc8x251g2d 4135f?8051?11/06 instruction set summary this section contains tables that summarize the instruction set. for each instruction there is a short description, its length in bytes, and its execution time in states (one state time is equal to two system clock cycles). there are two concurr ent processes limiting the effective instruction throughput: ? instruction fetch ? instruction execution table 20 to table 32 assume code executing from on-chip memory, then the cpu is fetching 16-bit at a time and this is never limiting the execution speed. if the code is fetched from external memory, a pre-fetch queue will store instructions ahead of execution to optimize the memory bandwidth usage when slower instructions are executed. however, the effective speed may be limited depending on the average size of instructions (for the considered section of the program flow). the maximum aver- age instruction throughput is provided by table 14 depending on the external memory configuration (from page mode to non-page mode and the maximum number of wait states). if the average size of instructions is not an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer values. table 14. minimum number of states per instruction for given average sizes if the average execution time of the considered instructions is larger than the number of states given by table 14, this larger value will prevail as the limiting factor. otherwise, the value from table 14 must be taken. this is providing a fair estimation of the execu- tion speed but only the actual code execution can provide the final value. notation for instruction operands table 15 to table 19 provide notation for instruction operands. table 15. notation for direct addressing average size of instructions (bytes) page mode (states) non-page mode (states) 0 wait state 1 wait state 2 wait states 3 wait states 4 wait states 1123456 224681012 3 3 6 9 12 15 18 44812162024 5 5 10 15 20 25 30 direct address description c251 c51 dir8 a direct 8-bit address. this can be a memory address (00h-7fh) or a sfr address (80h-ffh). it is a byte (default), word or double word depending on the other operand. 33 dir16 a 16-bit memory address (00:0000h-00:ffffh) used in direct addressing. 3? 22 at/tsc8x251g2d 4135f?8051?11/06 table 16. notation for immediate addressing table 17. notation for bit addressing table 18. notation for destination in control instructions immediate address description c251 c51 #data an 8-bit constant that is immediately addressed in an instruction 3 3 #data16 a 16-bit constant that is immediately addressed in an instruction 3 ? #0data16 #1data16 a 32-bit constant that is immediat ely addressed in an instruction. the upper word is filled with zeros (#0data16) or ones (#1data16). 3? #short a constant, equal to 1, 2, or 4, that is immediately addressed in an instruction. 3? direct address description c251 c51 bit51 a directly addressed bit (bit number = 00h-ffh) in memory or an sfr. bits 00h-7fh are the 128 bits in byte locations 20h-2fh in the on-chip ram. bits 80h-ffh are the 128 bits in the 16 sfrs with addresses that end in 0h or 8h, s:80h, s:88h, s:90h,..., s:f0h, s:f8h. ? 3 bit a directly addressed bit in me mory locations 00:0020h-00:007fh or in any defined sfr. 3 direct address description c251 c51 rel a signed (two?s complement) 8-bit relative address. the destination is -128 to +127 bytes relative to the next instruction?s first byte. 33 addr11 an 11-bit target address. the target is in the same 2-kbyte block of memory as the next instruction?s first byte. ?3 addr16 a 16-bit target address. the target can be anywhere within the same 64-kbyte region as the next instruction?s first byte. ?3 addr24 a 24-bit target address. the target can be anywhere within the 16- mbyte address space. 3? 23 at/tsc8x251g2d 4135f?8051?11/06 table 19. notation for register operands register description c251 c51 at ri a memory location (00h-ffh) addressed indirectly via byte registers r0 or r1 ?3 rn n byte register r0-r7 of the currently selected register bank byte register index: n = 0-7 ?3 rm rmd rms m, md, ms byte register r0-r15 of the currently selected register file destination register source register byte register index: m, md, ms = 0-15 3 ? wrj wrjd wrjs at wrj at wrj +dis16 j, jd, js word register wr0, wr2, ..., wr30 of the currently selected register file destination register source register a memory location (00:0000h-00:ffffh) addressed indirectly through word register wr0-wr30, is the target address for jump instructions. a memory location (00:0000h-00:ffffh) addressed indirectly through word register (wr0-wr30) + 16-bit signed (two?s complement) displacement value word register index: j, jd, js = 0-30 3 ? drk drkd drks at drk at drk +dis16 k, kd, ks dword register dr0, dr4, ..., dr28, dr56, dr60 of the currently selected register file destination register source register a memory location (00:0000h-ff:ffffh) addressed indirectly through dword register dr0-dr28, dr56 and dr60, is the target address for jump instruction a memory location (00:0000h-ff:ffffh) addressed indirectly through dword register (dr0-dr28, dr56, dr60) + 16-bit (two?s complement) signed displacement value dword register index: k, kd, ks = 0, 4, 8..., 28, 56, 60 3 ? 24 at/tsc8x251g2d 4135f?8051?11/06 size and execution time for instruction families table 20. summary of add and subtract instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x = 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 3. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). addadd 25 at/tsc8x251g2d 4135f?8051?11/06 4. if this instruction addresses external memory location, add 2(n+2) to the number of states (n: number of wait states). table 21. summary of increment and decrement instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x = 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sfr. incrementinc 26 at/tsc8x251g2d 4135f?8051?11/06 table 22. summary of compare instructions notes: 1. if this instruction addresses an i/o port (px, x = 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 2. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). 3. if this instruction addresses external memory location, add 2(n+2) to the number of states (n: number of wait states). comparecmp 27 at/tsc8x251g2d 4135f?8051?11/06 logical and (1) anl 28 at/tsc8x251g2d 4135f?8051?11/06 notes: 1. logical instructions that affect a bit are in table 27. 2. a shaded cell denotes an instruction in the c51 architecture. 3. if this instruction addresses an i/o port (px, x = 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sf r. 4. if this instruction addresses an i/o port (px, x = 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sf r. 5. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). 6. if this instruction addresses external memory location, add 2(n+2) to the number of states (n: number of wait states). table 23. summary of logical instructions (2/2) note: 1. a shaded cell denotes an instruction in the c51 architecture. shift left logicalsll 29 at/tsc8x251g2d 4135f?8051?11/06 table 24. summary of multiply, divide and decimal-adjust instructions note: 1. a shaded cell denotes an instruction in the c51 architecture. multiplymul ab(b:a) (a) (b) mul 30 at/tsc8x251g2d 4135f?8051?11/06 table 25. summary of move instructions (1/3) notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. extended memory addressed is in the region specified by dpxl (reset value = 01h). 3. if this instruction addresses external memory location, add n+1 to the number of states (n: number of wait states). 4. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). move to high wordmovh 31 at/tsc8x251g2d 4135f?8051?11/06 table 26. summary of move instructions (2/3) notes: 1. instructions that move bits are in table 27. 2. move instructions from the c51 architecture. 3. if this instruction addresses an i/o port (px, x = 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 4. apply note 3 for each dir8 operand. move (1) mov 32 at/tsc8x251g2d 4135f?8051?11/06 move (1) mov 33 at/tsc8x251g2d 4135f?8051?11/06 notes: 1. instructions that move bits are in table 27. 2. move instructions unique to the c251 architecture. 3. if this instruction addresses an i/o port (px, x = 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sf r. 4. if this instruction addresses external memory location, add n+2 to the number of states (n: number of wait states). 5. if this instruction addresses external memory location, add 2(n+1) to the number of states (n: number of wait states). 6. if this instruction addresses external memory location, add 4(n+2) to the number of states (n: number of wait states). mov wrj, at wrj +dis24 indirect with 16-bit displacement (16m) to word register 5 8 (5) 47 (5) mov at wrj +dis16, rm byte register to indirect with 16-bit displacement (64k) 5 6 (4) 45 (4) mov at wrj +dis16, wrj word register to indirect with 16-bit displacement (64k) 5 7 (5) 46 (5) mov at drk +dis24, rm byte register to indirect with 16-bit displacement (16m) 5 7 (4) 46 (4) mov at drk +dis24, wrj word register to indirect with 16-bit displacement (16m) 5 8 (5) 47 (5) 34 at/tsc8x251g2d 4135f?8051?11/06 table 27. summary of bit instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x = 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 3. if this instruction addresses an i/o port (px, x = 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sfr. clear bitclr 35 at/tsc8x251g2d 4135f?8051?11/06 table 28. summary of exchange, push and pop instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. if this instruction addresses an i/o port (px, x = 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 3. if this instruction addresses an i/o port (px, x = 0-3), add 2 to the number of states. add 3 if it addresses a peripheral sfr. exchange bytesxch a, 36 at/tsc8x251g2d 4135f?8051?11/06 table 29. summary of conditional jump instructions (1/2) notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. states are given as jump not-taken/taken. 3. in internal execution only, add 1 to the number of states of the ?jump taken? if the des- tination address is internal and odd. jump conditional on statusjcc rel(pc) (pc) + size (instr); if [cc] then (pc) (pc) + rel mnemonic 37 at/tsc8x251g2d 4135f?8051?11/06 table 30. summary of conditional jump instructions (2/2) notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. states are given as jump not-taken/taken. 3. if this instruction addresses an i/o port (px, x = 0-3), add 1 to the number of states. add 2 if it addresses a peripheral sfr. 4. if this instruction addresses an i/o port (px, x = 0-3), add 2 to the number of states. jump if bitjb 38 at/tsc8x251g2d 4135f?8051?11/06 add 3 if it addresses a peripheral sfr. 5. if this instruction addresses an i/o port (px, x = 0-3), add 3 to the number of states. add 5 if it addresses a peripheral sfr. 6. in internal execution only, add 1 to the number of states of the ?jump taken? if the des- tination address is internal and odd. table 31. summary of unconditional jump instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. in internal execution only, add 1 to the number of states if the destination address is internal and odd. 3. add 2 to the number of states if the destination address is external. 4. add 3 to the number of states if the destination address is external. absolute jumpajmp 39 at/tsc8x251g2d 4135f?8051?11/06 table 32. summary of call and return instructions notes: 1. a shaded cell denotes an instruction in the c51 architecture. 2. in internal execution only, add 1 to the number of states if the destination/return address is internal and odd. 3. add 2 to the number of states if the destination address is external. 4. add 5 to the number of states if intr = 1. absolute callacall 40 at/tsc8x251g2d 4135f?8051?11/06 programming and verifying non-volatile memory internal features the internal non-volatile memory of the tsc80251g2d derivatives contains five differ- ent areas: ? code memory ? configuration bytes ?lock bits ? encryption array ? signature bytes eprom/otprom devices all the internal non-volatile memory but the signature bytes of the tsc87251g2d prod- ucts is made of eprom cells. the signature bytes of the tsc87251g2d products are made of mask rom. the tsc87251g2d products are programmed and verified in the same manner as atmel?s tsc87251g1a, using a single-pulse algorithm, which programs at v pp = 12.75v using only one 100 s pulse per byte. this results in a programming time of less than 10 seconds for the 32 kilobytes on-chip code memory. the eprom of the tsc87251g2d products in window package is erasable by ultra- violet radiation (1) (uv). uv erasure set all the eprom memory cells to one and allows reprogramming. the quartz window must be covered with an opaque label (2) when the device is in operation. this is not so much to protect the eprom array from inadvertent erasure, as to protect the ram and other on-chip logic. allowing light to impinge on the silicon die during device operation may cause a logical malfunction. the tsc87251g2d products in plastic packages are one time programmable (otp). an eprom cell cannot be reset by uv once programmed to zero. notes: 1. the recommended erasure procedure is exposure to ultra-violet light (at 2537 ?) to an integrated dose of at least 20 w-sec/cm 2 . exposing the eprom to an ultra-violet lamp of 12000 w/cm 2 rating for 30 minutes should be sufficient. 2. erasure of the eprom begins to occur when the chip is exposed to light wavelength shorter than 4000 ?. since sunlight and fluorescent light have wavelength in this range, exposure to these light sources over an extended time (1 week in sunlight or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. mask rom devices all the internal non-volatile memory of tsc83251g2d products is made of mask rom cells. they can only be verified by the user, using the same algorithm as the eprom/otprom devices. romless devices the tsc80251g2d products do not include on-chip configuration bytes, code memory and encryption array. they only include signature bytes made of mask rom cells which can be read using the same algorithm as the eprom/otprom devices. security features in some microcontroller applications, it is desirable that the user?s program code be secured from unauthorized access. the tsc83251g2d and tsc87251g2d offer two kinds of protection for program code stored in the on-chip array: ? program code in the on-chip code memory is encrypted when read out for verification if the encryption array isprogrammed. ? a three-level lock bit system restricts external access to the on-chip code memory. 41 at/tsc8x251g2d 4135f?8051?11/06 lock bit system the tsc87251g2d products implement 3 levels of security for user?s program as described in table 33. the tsc83251g2d products implement only the first level of security. level 0 is the level of an erased part and does not enable any security features. level 1 locks the programming of the user?s internal code memory, the configuration bytes and the encryption array. level 2 locks the verifying of the user?s internal code memory. it is always possible to verify the configuration bytes and the lock bits. it is not possible to verify the encryp- tion array. level 3 locks the external execution. table 33. lock bits programming notes: 1. returns encrypted data if encryption array is programmed. 2. returns non encrypted data. 3. x means don?t care. level 2 always enables level 1, and level 3 always enables levels 1 and 2. the security level may be verified according to table 34. table 34. lock bits verifying note: 1. x means don?t care. encryption array the tsc83251g2d and tsc87251g2d products include a 128-byte encryption array located in non-volatile memory outside the memory address space. during verification of the on-chip code memory, the seven low-order address bits also address the encryp- tion array. as the byte of the code memory is read, it is exclusive-nor?ed (xnor) with the key byte from the encryption array. if the encryption array is not programmed (still all 1s), the user program code is placed on the data bus in its original, unencrypted form. if the encryption array is programmed with key bytes, the user program code is encrypted and cannot be used without knowledge of the key byte sequence. level lock bits lb[2:0] internal execution external execution verification programming external prom read (movc) 0 000 enable enable enable (1) enable enable (2) 1 001 enable enable enable (1) disable disable 2 01x (3) enable enable disable disable disable 31xx (3) enable disable disable disable disable level lock bits data (1) 0 xxxxx000 1 xxxxx001 2 xxxxx01x 3 xxxxx1xx 42 at/tsc8x251g2d 4135f?8051?11/06 to preserve the secrecy of the encryption key byte sequence, the encryption array can not be verified. notes: 1. when a movc instruction is executed, the content of the rom is not encrypted. in order to fully protect the user program code, the lock bit level 1 (see table 33) must always be set when encryption is used. 2. if the encryption feature is implemented, the portion of the on-chip code memory that does not contain program code should be filled with ?random? byte values to prevent the encryption key sequence from being revealed. signature bytes the tsc80251g2d derivatives contain factory-programmed signature bytes. these bytes are located in non-volatile memory outside the memory address space at 30h, 31h, 60h and 61h. to read the signature bytes, perform the procedure described in sec- tion verify algorithm, using the verify signature mode (see table 37). signature byte values are listed in table 35. table 35. signature bytes (electronic id) programming algorithm figure 6 shows the hardware setup needed to program the tsc87251g2d eprom/otprom areas: ? the chip has to be put under reset and maintained in this state until completion of the programming sequence. ? psen# and the other control signals (ale and port 0) have to be set to a high level. ? then psen# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state until the completion of the programming sequence (see below). ? the voltage on the ea# pin must be set to v dd . ? the programming mode is selected according to the code applied on port 0 (see table 36). it has to be applied until the completion of this programming operation. ? the programming address is applied on ports 1 and 3 which are respectively the most significant byte (msb) and the least significant byte (lsb) of the address. ? the programming data are applied on port 2. ? the eprom programming is done by raising the voltage on the ea# pin to v pp , then by generating a low level pulse on ale/prog# pin. ? the voltage on the ea# pin must be lowered to v dd before completing the programming operation. ? it is possible to alternate programming and verifying operation (see paragraph verify algorithm). please make sure the voltage on the ea# pin has actually been lowered to v dd before performing the verifying operation. signature address signature data vendor atmel 30h 58h architecture c251 31h 40h memory 32 kilobytes eprom or otprom 60h f7h 32 kilobytes maskrom or romless 77h revision tsc80251g2d derivative 61h fdh 43 at/tsc8x251g2d 4135f?8051?11/06 ? psen# and the other control signals have to be released to complete a sequence of programming operations or a sequence of programming and verifying operations. figure 6. setup for programming table 36. programming modes notes: 1. signature bytes are not user-programmable. 2. the ale/prog# pulse waveform is shown in figure 23 page 59. verify algorithm figure 7 shows the hardware setup needed to verify the tsc87251g2d eprom/otprom or tsc83251g2d rom areas: ? the chip has to be put under reset and maintained in this state until the completion of the verifying sequence. ? psen# and the other control signals (ale and port 0) have to be set to a high level. ? then psen# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state until the completion of the verifying sequence (see below). ? the voltage on the ea# pin must be set to v dd and ale must be set to a high level. ? the verifying mode is selected according to the code applied on port 0. it has to be applied until the completion of this verifying operation. ? the verifying address is applied on ports 1 and 3 which are respectively the msb and the lsb of the address. rom area (1) rst ea#/vpp psen # ale/prog# (2) p0 p2 p1(msb) p3(lsb) on-chip code memory 1v pp 0 1 pulse 68h data 16-bit address 0000h-7fffh (32 kilobytes) configuration bytes 1v pp 0 1 pulse 69h data config0: fff8h config1: fff9h lock bits 1 v pp 0 1 pulse 6bh x lb0: 0001h lb1: 0002h lb2: 0003h encryption array 1 v pp 0 1 pulse 6ch data 0000h-007fh vdd psen# ale/prog# ea#/vpp xtal1 vdd 4 to 12 mhz rst vpp 100 ms pulses vss/vss1/vss2 mode vdd a[7:0] a[14:8] data p0[7:0] p3[7:0] p1[7:0] p2[7:0] tsc87251g2d 44 at/tsc8x251g2d 4135f?8051?11/06 ? then device is driving the data on port 2. ? it is possible to alternate programming and verification operation (see paragraph programming algorithm). please make sure the voltage on the ea# pin has actually been lowered to v dd before performing the verifying operation. ? psen# and the other control signals have to be released to complete a sequence of verifying operations or a sequence of programming and verifying operations. table 37. verifying modes notes: 1. to preserve the secrecy of on-chip code memory when encrypted, the encryption array can not be verified. figure 7. setup for verifying rom area (1) rst ea#/vpp psen# ale/prog# p0 p2 p1(msb) p3(lsb) on-chip code memory 1 1 0 1 28h data 16-bit address 0000h-7fffh (32 kilobytes) configuration bytes 1 1 0 1 29h data config0: fff8h config1: fff9h lock bits 1 1 0 1 2bh data 0000h signature bytes 1 1 0 1 29h data 0030h, 0031h, 0060h, 0061h vdd psen# ale/prog# ea#/vpp xtal1 vdd 4 to 12 mhz rst vss/vss1/vss2 mode vdd a[7:0] a[14:8] p0[7:0] p3[7:0] p1[7:0] tsc8x251g2d p2[7:0] data 45 at/tsc8x251g2d 4135f?8051?11/06 ac characteristics - commercial & industrial ac characteristics - external bus cycles definition of symbols table 38. external bus cycles timing symbol definitions timings test conditions: capacitive load on all pins = 50 pf. table 39 and table 40 list the ac timing parameters for the tsc80251g2d derivatives with no wait states. external wait states can be added by extending psen#/rd#/wr# and or by extending ale. in these tables, note 2 marks parameters affected by one ale wait state, and note 3 marks parameters affected by psen#/rd#/wr# wait states. figure 8 to figure 13 show the bus cycles with the timing parameters. signals conditions a address h high d data in l low l ale v valid q data out x no longer valid r rd#/psen# z floating wwr# 46 at/tsc8x251g2d 4135f?8051?11/06 table 39. bus cycles ac timings; v dd = 4.5 to 5.5 v, t a = -40 to 85 c notes: 1. specification for psen# are identical to those for rd#. 2. if a wait state is added by extending ale, add 2t osc. 3. if wait states are added by extending rd#/psen#/wr#, add 2nt osc (n = 1..3). symbol parameter 12 mhz 16 mhz 24 mhz unit min max min max min max t osc 1/f osc 83 62 41 ns t lhll ale pulse width 78 58 38 ns (2) t av ll address valid to ale low 78 58 37 ns (2) t llax address hold after ale low 19 11 3 ns t rlrh (1) rd#/psen# pulse width 162 121 78 ns (3) t wlwh wr# pulse width 165 124 81 ns (3) t llrl (1) ale low to rd#/psen# low 22 14 6 ns t lhax ale high to address hold 99 70 40 ns (2) t rldv (1) rd#/psen# low to valid data 146 104 61 ns (3) t rhdx (1) data hold after rd#/psen# high 0 0 0 ns t rhax (1) address hold after rd#/psen# high 000ns t rlaz (1) rd#/psen# low to address float 0 0 0 ns t rhdz1 instruction float after rd#/psen# high 45 40 30 ns t rhdz2 data float after rd#/psen# high 215 165 115 ns t rhlh1 rd#/psen# high to ale high (instruction) 49 43 31 ns t rhlh2 rd#/psen# high to ale high (data) 215 169 115 ns t whlh wr# high to ale high 215 169 115 ns t avdv1 address (p0) valid to valid data in 250 175 105 ns (2)(3) t avdv2 address (p2) valid to valid data in 306 223 140 ns (2)(3) t avdv3 address (p0) valid to valid instruction in 150 109 68 ns (3) t axdx data hold after address hold 0 0 0 ns t avrl (1) address valid to rd# low 100 70 40 ns (2) t av wl1 address (p0) valid to wr# low 100 70 40 ns (2) t av wl2 address (p2) valid to wr# low 158 115 74 ns (2) t whqx data hold after wr# high 90 69 32 ns t qvwh data valid to wr# high 133 102 72 ns (3) t whax wr# high to address hold 167 125 84 ns 47 at/tsc8x251g2d 4135f?8051?11/06 table 40. bus cycles ac timings; v dd = 2.7 to 5.5 v, t a = -40 to 85 c notes: 1. specification for psen# are identical to those for rd#. 2. if a wait state is added by extending ale, add 2t osc. 3. if wait states are added by extending rd#/psen#/wr#, add 2nt osc (n = 1..3). symbol parameter 12 mhz 16 mhz unit min max min max t osc 1/f osc 83 62 ns t lhll ale pulse width 72 52 ns (2) t av ll address valid to ale low 71 51 ns (2) t llax address hold after ale low 14 6 ns t rlrh (1) rd#/psen# pulse width 163 121 ns (3) t wlwh wr# pulse width 165 124 ns (3) t llrl (1) ale low to rd#/psen# low 17 11 ns t lhax ale high to address hold 90 57 ns (2) t rldv (1) rd#/psen# low to valid data 133 92 ns (3) t rhdx (1) data hold after rd#/psen# high 0 0 ns t rhax (1) address hold after rd#/psen# high 0 0 ns t rlaz (1) rd#/psen# low to address float 0 0 ns t rhdz1 instruction float after rd#/psen# high 59 48 ns t rhdz2 data float after rd#/psen# high 225 175 ns t rhlh1 rd#/psen# high to ale high (instruction) 60 47 ns t rhlh2 rd#/psen# high to ale high (data) 226 172 ns t whlh wr# high to ale high 226 172 ns t avdv1 address (p0) valid to valid data in 289 160 ns (2)(3) t avdv2 address (p2) valid to valid data in 296 211 ns (2)(3) t avdv3 address (p0) valid to valid instruction in 144 98 ns (3) t axdx data hold after address hold 0 0 ns t avrl (1) address valid to rd# low 111 64 ns (2) t av wl1 address (p0) valid to wr# low 111 64 ns (2) t av wl2 address (p2) valid to wr# low 158 116 ns (2) t whqx data hold after wr# high 82 66 ns t qvwh data valid to wr# high 135 103 ns (3) t whax wr# high to address hold 168 125 ns 48 at/tsc8x251g2d 4135f?8051?11/06 waveforms in non-page mode figure 8. external bus cycle: code fetch (non-page mode) note: 1. the value of this parameter depends on wait states. see table 39 and table 40. figure 9. external bus cycle: data read (non-page mode) note: 1. the value of this parameter depends on wait states. see table 39 and table 40. t avdv2 (1) t avdv1 (1) t llax t rhdz1 t rhdx t rhax t avrl (1) p2/a16/a17 p0 psen# ale tlhll(1) trlrh(1) instruction in a15:8/a16/a17 t rlaz tllrl(1) trhlh1 trldv(1) t avll (1) t lhax (1) a7:0 d7:0 t avdv2 (1) t avdv1 (1) t llax t rhax t rhdx t rhdz2 t avll (1) t avrl (1) p2/a16/a17 p0 rd#/psen# ale tlhll(1) trlrh(1) t lhax (1) data in a15:8/a16/a17 t rlaz tllrl(1) trhlh2 trldv(1) d7:0 a7:0 49 at/tsc8x251g2d 4135f?8051?11/06 figure 10. external bus cycle: data write (non-page mode) note: 1. the value of this parameter depends on wait states. see table 39 and table 40. waveforms in page mode figure 11. external bus cycle: code fetch (page mode) note: 1. the value of this parameter depends on wait states. see table 39 and table 40. 2. a page hit (i.e., a code fetch to the same 256-byte ?page? as the previous code fetch) requires one state (2t osc ); a page miss requires two states (4t osc ). 3. during a sequence of page hits, psen# remains low until the end of the last page-hit cycle. t whlh t avwl2 (1) t avwl1 (1) t lhax (1) t llax t whqx t whax p2/a16/a17 p0 wr# ale tlhll(1) twlwh(1) data out a15:8/a16/a17 tavll(1) t qvwh a7:0 d7:0 t llax t avdv2 (1) t avdv1 (1) t lhax (1) t avrl (1) t rhdz1 t rlaz t axdx t avdv3 (1) p0/a16/a17 p2 psen# (3) ale tlhll(1) a7:0/a16/a17 tavll(1) tllrl(1) trldv(1) page miss(2) page hit(2) t rhax a7:0/a16/a17 d7:0 d7:0 a15:8 instruction in instruction in t rhdx 50 at/tsc8x251g2d 4135f?8051?11/06 figure 12. external bus cycle: data read (page mode) note: 1. the value of this parameter depends on wait states. see table 39 and table 40. figure 13. external bus cycle: data write (page mode) note: 1. the value of this parameter depends on wait states. see table 39 and table 40. ac characteristics - real-time synchronous wait state definition of symbols table 41. real-time synchronous wait timing symbol definitions t avdv2 (1) t avdv1 (1) t llax t rhax t rhdx t rhdz2 t av ll (1) t avrl (1) p0/a16/a17 p2 rd#/psen# ale tlhll(1) trlrh(1) t lhax (1) data in a7:0/a16/a17 t rlaz tllrl(1) trhlh2 trldv(1) d7:0 a15:8 t whlh t avwl2 (1) t avwl1 (1) t lhax (1) t llax t whqx t whax p0/a16/a17 p2 wr# ale tlhll(1) twlwh(1) data out a7:0/a16/a17 tavll(1) t qvwh a15:8 d7:0 signals conditions c wclk l low r rd#/psen# v valid w wr# x no longer valid ywait# 51 at/tsc8x251g2d 4135f?8051?11/06 timings table 42. real-time synchronous wait ac timings; v dd = 2.7 to 5.5 v, t a = -40 to 85 c waveforms figure 14. real-time synchronous wait state: code fetch/data read figure 15. real-time synchronous wait state: data write symbol parameter min max unit t clyv wait clock low to wait set-up 0 t osc - 20 ns t clyx wait hold after wait clock low 2wt osc + 5 (1+2w)t osc - 20 ns t rlyv psen#/rd# low to wait set-up 0 t osc - 20 ns t rlyx wait hold after psen#/rd# low 2wt osc + 5 (1+2w)t osc - 20 ns t wlyv wr# low to wait set-up 0 t osc - 20 ns t wlyx wait hold after wr# low 2wt osc + 5 (1+2w)t osc - 20 ns state 1 state 2 state 3 state 1 (next cycle) t rlyx max t rlyx min t rlyv t clyv t clyx max p2 rd#/psen# ale wclk p0 wait# t clyx min rd#/psen# stretched a15:8 a7:0 d7:0 stretched a15:8 stretched a7:0 state 1 state 2 state 3 state 1 (next cycle) t wlyx max t wlyx min t wlyv t clyv t clyx max p2 rd#/psen# ale wclk p0 wait# t clyx min wr# stretched a7:0 d7:0 stretched a15:8 stretched 52 at/tsc8x251g2d 4135f?8051?11/06 ac characteristics - real-time asynchronous wait state definition of symbols table 43. real-time asynchronous wait timing symbol definitions timings table 44. real-time asynchronous wait ac timings; v dd = 2.7 to 5.5 v, t a = -40 to 85 c note: 1. n is the number of wait states added (n 1). waveforms figure 16. real-time asynchronous wait state timings ac characteristics - serial port in shift register mode definition of symbols table 45. serial port timing symbol definitions signals conditions s psen#/rd#/wr# l low y await# v valid x no longer valid symbol parameter min max unit t slyv psen#/rd#/wr# low to wait set-up t osc - 10 ns t slyx wait hold after psen#/rd#/wr# low (2n-1)t osc + 10 ns (1) t slyv t slyx rd#/psen#/wr# await# signals conditions d data in h high q data out l low x clock v valid x no longer valid 53 at/tsc8x251g2d 4135f?8051?11/06 timings table 46. serial port ac timing -shift register mode; v dd = 2.7 to 5.5 v, t a = -40 to 85 c note: 1. for high speed versions only. waveforms figure 17. serial port waveforms - shift register mode note: 1. ti and ri are set during s1p1 of the peripheral cycle following the shift of the eight bit. symbol parameter 12 mhz 16 mhz 24 mhz (1) unit min max min max min max t xlxl serial port clock cycle time 998 749 500 ns t qvxh output data setup to clock rising edge 833 625 417 ns t xhqx output data hold after clock rising edge 165 124 82 ns t xhdx input data hold after clock rising edge 000ns t xhdv clock rising edge to input data valid 974 732 482 ns t xlxl t xhdv t xhdx t qvxh t xhqx set ti (1) set ri (1) valid valid valid valid valid valid valid valid rxd (in) rxd (out) txd 0 1 2 3 4 5 6 7 54 at/tsc8x251g2d 4135f?8051?11/06 ac characteristics - sslc: twi interface timings table 47. twi interface ac timing; v dd = 2.7 to 5.5 v, t a = -40 to 85 c notes: 1. at 100 kbit/s. at other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. spikes on the sda and scl lines with a duration of less than 3t clcl will be filtered out. maximum capacitance on bus-lines sda and scl = 400 pf. 4. t clcl = t osc = one oscillator clock period. waveforms figure 18. twi waveforms symbol parameter input min max output min max t hd ; sta start condition hold time 14t clcl (4) 4.0 s (1) t low scl low time 16t clcl (4) 4.7 s (1) t high scl high time 14t clcl (4) 4.0 s (1) t rc scl rise time 1 s- (2) t fc scl fall time 0.3 s0.3 s (3) t su ; dat1 data set-up time 250 ns 20t clcl (4) - t rd t su ; dat2 sda set-up time (before repeated start condition) 250 ns 1 s (1) t su ; dat3 sda set-up time (before stop condition) 250 ns 8t clcl (4) t hd ; dat data hold time 0 ns 8t clcl (4) - t fc t su ; sta repeated start set-up time 14t clcl (4) 4.7 s (1) t su ; sto stop condition set-up time 14t clcl (4) 4.0 s (1) t buf bus free time 14t clcl (4) 4.7 s (1) t rd sda rise time 1 s - (2) t fd sda fall time 0.3 s0.3 s (3) t su ;sta t su ;dat2 t hd ;sta t high t low sda (input/output) 0.3 v dd 0.7 v dd t buf t su ;sto 0.7 v dd 0.3 v dd t rd t fd t rc t fc scl (input/output) t su ;dat1 t hd ;dat t su ;dat3 start or repeated start condition start condition stop condition repeated start condition 55 at/tsc8x251g2d 4135f?8051?11/06 ac characteristics - sslc: spi interface definition of symbols table 48. spi interface timing symbol definitions signals conditions c clock h high i data in l low o data out v valid s ss# x no longer valid z floating 56 at/tsc8x251g2d 4135f?8051?11/06 timings table 49. spi interface ac timing; v dd = 2.7 to 5.5 v, t a = -40 to 85 c notes: 1. capacitive load on all pins = 200 pf in slave mode. 2. the value of this parameter depends on software. 3. capacitive load on all pins = 100 pf in master mode. symbol parameter min max unit slave mode (1) t chch clock period 8 t osc t chcx clock high time 3.2 t osc t clcx clock low time 3.2 t osc t slch , t slcl ss# low to clock edge 200 ns t ivcl , t ivch input data valid to clock edge 100 ns t clix , t chix input data hold after clock edge 100 ns t clov, t chov output data valid after clock edge 100 ns t clox , t chox output data hold time after clock edge 0 ns t clsh , t chsh ss# high after clock edge 0 ns t ivcl , t ivch input data valid to clock edge 100 ns t clix , t chix input data hold after clock edge 100 ns t slov ss# low to output data valid 130 ns t shox output data hold after ss# high 130 ns t shsl ss# high to ss# low (2) t ilih input rise time 2 s t ihil input fall time 2 s t oloh output rise time 100 ns t ohol output fall time 100 ns master mode (3) t chch clock period 4 t osc t chcx clock high time 1.6 t osc t clcx clock low time 1.6 t osc t ivcl , t ivch input data valid to clock edge 50 ns t clix , t chix input data hold after clock edge 50 ns t clov, t chov output data valid after clock edge 65 ns t clox , t chox output data hold time after clock edge 0 ns t ilih input data rise time 2 s t ihil input data fall time 2 s t oloh output data rise time 50 ns t ohol output data fall time 50 ns 57 at/tsc8x251g2d 4135f?8051?11/06 waveforms figure 19. spi master waveforms (sscpha = 0) note: 1. ss# handled by software. figure 20. spi master waveforms (sscpha = 1) note: 1. not defined but normally msb of character just received. miso (input) sck (sscpol = 0) (output) ss# (1) (output) sck (sscpol = 1) (output) mosi (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch miso (input) sck (sscpol = 0) (output) ss# (1) (output) sck (sscpol = 1) (output) mosi (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch 58 at/tsc8x251g2d 4135f?8051?11/06 figure 21. spi slave waveforms (sscpha = 0) note: 1. not defined but generally the lsb of the character which has just been received. figure 22. spi slave waveforms (sscpha = 1) ac characteristics - eprom programming and verifying definition of symbols table 50. eprom programming and verifying timing symbol definitions t slcl t slch t chcl t clch mosi (input) sck (sscpol = 0) (input) ss# (input) sck (sscpol = 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh t chcl t clch mosi (input) sck (sscpol = 0) (input) ss# (input) sck (sscpol = 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t clov t chov t clox t chox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh t slcl t slch signals conditions a address h high e enable: mode set on port 0 l low g program v valid q data out x no longer valid s supply (v pp ) z floating 59 at/tsc8x251g2d 4135f?8051?11/06 timings table 51. eprom programming ac timings; v dd = 4.5 to 5.5 v, t a = 0 to 40 c table 52. eprom verifying ac timings; v dd = 4.5 to 5.5 v, v dd = 2.7 to 5.5 v, t a = 0 to 40 c waveforms figure 23. eprom programming waveforms symbol parameter min max unit t osc xtal1 period 83.5 250 ns t avgl address setup to prog# low 48 t osc t ghax address hold after prog# low 48 t osc t dvgl data setup to prog# low 48 t osc t ghdx data hold after prog# 48 t osc t elsh enable high to v pp 48 t osc t shgl v pp setup to prog# low 10 s t ghsl v pp hold after prog# 10 s t sleh enable hold after v pp 0ns t glgh prog# width 90 110 s symbol parameter min max unit t osc xtal1 period 83.5 250 ns t avqv address to data valid 48 t osc t axqx address to data invalid 0 ns t elqv enable low to data valid 0 48 t osc t ehqz data float after enable 0 48 t osc t sleh t elsh t dvgl t shgl t av g l t ghax t ghdx t glgh t ghsl v pp v dd v ss p1 = a15:8 p3 = a7:0 p2 = d7:0 ea#/vpp ale/prog# p0 mode = 68h, 69h, 6bh or 6ch data address 60 at/tsc8x251g2d 4135f?8051?11/06 figure 24. eprom verifying waveforms ac characteristics - external clock drive and logic level references definition of symbols table 53. external clock timing symbol definitions timings table 54. external clock ac timings; v dd = 4.5 to 5.5 v, t a = -40 to +85 c waveforms figure 25. external clock waveform notes: 1. during ac testing, all inputs are driven at v dd -0.5 v for a logic 1 and 0.45 v for a logic 0. 2. timing measurements are made on all outputs at v ih min for a logic 1 and v il max for a logic 0. t ehqz t elqv t avqv t axqx p1 = a15:8 p3 = a7:0 p2 = d7:0 p0 address mode = 28h, 29h or 2bh data signals conditions c clock h high l low x no longer valid symbol parameter min max unit f osc oscillator frequency 24 mhz t chcx high time 10 ns t clcx low time 10 ns t clch rise time 3 ns t chcl fall time 3 ns 0.45 v t clcl v dd - 0.5 v ih1 v il t chcx t clch t chcl t clcx 61 at/tsc8x251g2d 4135f?8051?11/06 figure 26. ac testing input/output waveforms note: for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol /i oh = 20 ma. figure 27. float waveforms 0.45 v v dd - 0.5 0.2 v dd + 0.9 0.2 v dd - 0.1 v ih min v il max inputs outputs v load v oh - 0.1 v v ol + 0.1 v v load + 0.1 v v load - 0.1 v timing reference points 62 at/tsc8x251g2d 4135f?8051?11/06 absolute maximum rating and operating conditions absolute maximum ratings storage temperature ......................................... -65 to +150 c voltage on any other pin to vss ........................ -0.5 to +6.5 v i ol per i/o pin ................................................................ 15 ma power dissipation ........................................................... 1.5 w ambient temperature under bias commercial..............................................................0 to +70 c industrial .............................................................. -40 to +85 c automotive........................................................... -40 to +85 c v dd high speed versions.............................................. 4.5 to 5.5 v low voltage versions............................................. 2.7 to 5.5 v *notice: stressing the device beyond the ?absolute maxi- mum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. 63 at/tsc8x251g2d 4135f?8051?11/06 dc characteristics high speed versions - commercial, industrial, and automotive table 55. dc characteristics; v dd = 4.5 to 5.5 v, t a = -40 to +85 c symbol parameter min typical (4) max units test conditions v il input low voltage (except ea#, scl, sda) -0.5 0.2v dd - 0.1 v v il1 (5) input low voltage (scl, sda) -0.5 0.3v dd v v il2 input low voltage (ea#) 00.2v dd - 0.3 v v ih input high voltage (except xtal1, rst, scl, sda) 0.2v dd + 0.9 v dd + 0.5 v v ih1 (5) input high voltage (xtal1, rst, scl, sda) 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1, 2, 3) 0.3 0.45 1.0 v i ol = 100 a (1)(2) i ol = 1.6 ma (1)(2) i ol = 3.5 ma (1)(2) v ol1 output low voltage (ports 0, ale, psen#, port 2 in page mode during external address) 0.3 0.45 1.0 v i ol = 200 a (1)(2) i ol = 3.2 ma (1)(2) i ol = 7.0 ma (1)(2) v oh output high voltage (ports 1, 2, 3, ale, psen#) v dd - 0.3 v dd - 0.7 v dd - 1.5 v i oh = -10 a (3) i oh = -30 a (3) i oh = -60 a (3) v oh1 output high voltage (port 0, port 2 in page mode during external address) v dd - 0.3 v dd - 0.7 v dd - 1.5 v i oh = -200 a i oh = -3.2 ma i oh = -7.0 ma v ret v dd data retention limit 1.8 v i il0 logical 0 input current (ports 1, 2, 3) - 50 av in = 0.45 v i il1 logical 1 input current (nmi) + 50 av in = v dd i li input leakage current (port 0) 10 a0.45 v < v in < v dd i tl logical 1-to-0 transition current (ports 1, 2, 3 - await#) - 650 av in = 2.0 v r rst rst pull-down resistor 40 110 225 k c io pin capacitance 10 pf t a = 25 c i dd operating current 20 25 35 25 30 40 ma f osc = 12 mhz f osc = 16 mhz f osc = 24 mhz i dl idle mode current 5 6.5 9.5 8 10 14 ma f osc = 12 mhz f osc = 16 mhz f osc = 24 mhz i pd power-down current 2 20 av ret < v dd < 5.5 v v pp programming supply voltage 12.5 13 v t a = 0 to +40 c i pp programming supply current 75 ma t a = 0 to +40 c 64 at/tsc8x251g2d 4135f?8051?11/06 notes: 1. under steady-state (non-transient) conditions, i ol must be externally limited as follows: maximum iol per port pin: 10 ma maximum iol per 8-bit port:port 0 26 ma ports 1-3 15 ma maximum total iol for all: output pins 71 ma if iol exceeds the test conditions, vol may exceed the related specification. pins are not guar anteed to sink current greater t han the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen# to drop below the specification when the address lines are stabilizing. 4. typical values are obtained using v dd = 5 v and t a = 25 c. they are not tested and there is not guarantee on these values. 5. the input threshold voltage of scl and sda meets the twi specification, so an input voltage below 0.3v dd will be recog- nized as a logic 0 while an input voltage above 0.7v dd will be recognized as a logic 1. figure 28. i dd /i dl versus frequency; v dd = 4.5 to 5.5 v note: 1. the clock prescaler is not used: f osc = f xtal . max active mode (ma) typ active mode (ma) max idle mode (ma) typ idle mode (ma) 40 30 20 10 0 idd/idl (ma) frequency at xtal(1) (mhz) 2 4 6 8 10 12 14 16 18 20 22 24 65 at/tsc8x251g2d 4135f?8051?11/06 low voltage versions - commercial & industrial notes: 1. under steady-state (non-transient) conditions, i ol must be externally limited as follows: maximum iol per port pin: 10 ma maximum iol per 8-bit port: port 0 26 ma ports 1-315 ma table 56. dc characteristics; v dd = 2.7 to 5.5 v, t a = -40 to +85 c symbol parameter min typical (4) max units test conditions v il input low voltage (except ea#, scl, sda) -0.5 0.2v dd - 0.1 v v il1 (5) input low voltage (scl, sda) -0.5 0.3v dd v v il2 input low voltage (ea#) 00.2v dd - 0.3 v v ih input high voltage (except xtal1, rst, scl, sda) 0.2v dd + 0.9 v dd + 0.5 v v ih1 (5) input high voltage (xtal1, rst, scl, sda) 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1, 2, 3) 0.45 v i ol = 0.8 ma (1)(2) v ol1 output low voltage (ports 0, ale, psen#, port 2 in page mode during external address) 0.45 v i ol = 1.6 ma (1)(2) v oh output high voltage (ports 1, 2, 3, ale, psen#) 0.9v dd vi oh = -10 a (3) v oh1 output high voltage (port 0, port 2 in page mode during external address) 0.9v dd vi oh = -40 a v ret v dd data retention limit 1.8 v i il0 logical 0 input current (ports 1, 2, 3 - await#) - 50 av in = 0.45 v i il1 logical 1 input current (nmi) + 50 av in = v dd i li input leakage current (port 0) 10 a 0.45 v < v in < v dd i tl logical 1-to-0 transition current (ports 1, 2, 3) - 650 av in = 2.0 v r rst rst pull-down resistor 40 110 225 k c io pin capacitance 10 pf t a = 25 c i dd operating current 4 8 9 11 8 11 12 14 ma 5 mhz, v dd < 3.6 v 10 mhz, v dd < 3.6 v 12 mhz, v dd < 3.6 v 16 mhz, v dd < 3.6 v i dl idle mode current 0.5 1.5 2 3 1 4 5 7 ma 5 mhz, v dd < 3.6 v 10 mhz, v dd < 3.6 v 12 mhz, v dd < 3.6 v 16 mhz, v dd < 3.6 v i pd power-down current 1 10 av ret < v dd < 3.6 v 66 at/tsc8x251g2d 4135f?8051?11/06 maximum total iol for all:output pins71 ma if iol exceeds the test conditions, vol may exceed the related specification. pins are not guaranteed to sink current greater t han the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen# to drop below the specification when the address lines are stabilizing. 4. typical values are obtained using v dd = 3 v and t a = 25 c. they are not tested and there is not guarantee on these values. 5. the input threshold voltage of scl and sda meets the twi specification, so an input voltage below 0.3v dd will be recog- nized as a logic 0 while an input voltage above 0.7v dd will be recognized as a logic 1. figure 29. i dd /i dl versus x tal frequency; v dd = 2.7 to 3.6 v note: 1.the clock prescaler is not used: f osc = f xtal . i dd, i dl and i pd test conditions figure 30. i dd test condition, active mode max active mode (ma) typ active mode (ma) max idle mode (ma) typ idle mode (ma) 15 10 5 0 idd/idl (ma) frequency at xtal(1) (mhz) 2468 14 10 12 16 vdd xtal2 vdd clock signal rst vss tsc80251g2d ea# xtal1 vdd p0 (nc) idd vdd all other pins are unconnected 67 at/tsc8x251g2d 4135f?8051?11/06 figure 31. i dl test condition, idle mode figure 32. i pd test condition, power-down mode xtal2 vdd clock signal rst vss tsc80251g2d ea# xtal1 vdd p0 (nc) idl vdd all other pins are unconnected xtal2 vdd rst vss tsc80251g2d ea# xtal1 vdd p0 (nc) ipd vdd all other pins are unconnected 68 at/tsc8x251g2d 4135f?8051?11/06 packages list of packages ?pdil 40 ? cdil 40 with window ? plcc 44 ? cqpj 44 with window ? vqfp 44 (10x10) pdil 40 - mechanical outline figure 33. plastic dual in line table 57. pdil package size mm inch min max min max a - 5.08 - .200 a1 0.38 - .015 - a2 3.18 4.95 .125 .195 b 0.36 0.56 .014 .022 b1 0.76 1.78 .030 .070 c 0.20 0.38 .008 .015 d 50.29 53.21 1.980 2.095 e 15.24 15.87 .600 .625 e1 12.32 14.73 .485 .580 e 2.54 b.s.c. .100 b.s.c. ea 15.24 b.s.c. .600 b.s.c. eb - 17.78 - .700 l 2.93 3.81 .115 .150 d1 0.13 - .005 - 69 at/tsc8x251g2d 4135f?8051?11/06 cdil 40 with window - mechanical outline figure 34. ceramic dual in line table 58. cdil package size mm inch min max min max a - 5.71 - .225 b 0.36 0.58 .014 .023 b2 1.14 1.65 .045 .065 c 0.20 0.38 .008 .015 d - 53.47 - 2.105 e 13.06 15.37 .514 .605 e 2.54 b.s.c. .100 b.s.c. ea 15.24 b.s.c. .600 b.s.c. l 3.18 5.08 .125 .200 q 0.38 1.40 .015 .055 s1 0.13 - .005 - a 0 - 15 0 - 15 n40 70 at/tsc8x251g2d 4135f?8051?11/06 plcc 44 - mechanical outline figure 35. plastic lead chip carrier table 59. plcc package size mm inch min max min max a 4.20 4.57 .165 .180 a1 2.29 3.04 .090 .120 d 17.40 17.65 .685 .695 d1 16.44 16.66 .647 .656 d2 14.99 16.00 .590 .630 e 17.40 17.65 .685 .695 e1 16.44 16.66 .647 .656 e2 14.99 16.00 .590 .630 e 1.27 bsc .050 bsc g 1.07 1.22 .042 .048 h 1.07 1.42 .042 .056 j 0.51 - .020 - k 0.33 0.53 .013 .021 nd 11 11 ne 11 11 71 at/tsc8x251g2d 4135f?8051?11/06 cqpj 44 with window - mechanical outline figure 36. ceramic quad pack j table 60. cqpj package size mm inch min max min max a - 4.90 - .193 c 0.15 0.25 .006 .010 d - e 17.40 17.55 .685 .691 d1 - e1 16.36 16.66 .644 .656 e 1.27 typ .050 typ f 0.43 0.53 .017 .021 j 0.86 1.12 .034 .044 q 15.49 16.00 .610 .630 r 0.86 typ .034 typ n1 11 11 n2 11 11 72 at/tsc8x251g2d 4135f?8051?11/06 vqfp 44 (10x10) - mechanical outline figure 37. shrink quad flat pack (plastic) table 61. vqfp package size mm inch min max min max a - 1.60 - .063 a1 0.64 ref .025 ref a2 0.64 ref .025ref a3 1.35 1.45 .053 .057 d 11.90 12.10 .468 .476 d1 9.90 10.10 .390 .398 e 11.90 12.10 .468 .476 e1 9.90 10.10 .390 .398 j 0.05 - .002 6 l 0.45 0.75 .018 .030 e 0.80 bsc .0315 bsc f 0.35 bsc .014 bsc 73 4135f?8051?11/06 at/tsc8x251g2d ordering information at/tsc80251g2d romless at/tsc83251g2d 32 kilobytes maskrom part number rom description high speed versions 4.5 to 5.5 v, commercial and industrial tsc80251g2d-16cb romless 16 mhz, commercial 0 to 70 c, plcc 44 tsc80251g2d-24cb romless 24 mhz, commercial 0 to 70 c, plcc 44 tsc80251g2d-24ce romless 24 mhz, commercial 0 to 70 c, vqfp 44 tsc80251g2d-24ia romless 24 mhz, industrial -40 to 85 c, pdil 40 tsc80251g2d-24ib romless 24 mhz, industrial -40 to 85 c, plcc 44 at80251g2d-slsum romless 24 mhz, industrial & green -40 to 85 c, plcc 44 at80251g2d-3csum romless 24 mhz, industrial & green -40 to 85 c, pdil 40 at80251g2d-rltum romless 24 mhz, industrial & green -40 to 85 c, vqfp 44 low voltage versions 2.7 to 5.5 v tsc80251g2d-l16cb romless 16 mhz, commercial, plcc 44 tsc80251g2d-l16ce romless 16 mhz, commercial, vqfp 44 at80251g2d-slsul romless 16 mhz, industrial & green, plcc 44 at80251g2d-rltul romless 16 mhz, industrial & green, vqfp 44 part number (1) rom description high speed versions 4.5 to 5.5 v, commercial and industrial tsc251g2dxxx-16cb 32k maskrom 16 mhz, commercial 0 to 70 c, plcc 44 tsc251g2dxxx-24cb 32k maskrom 24 mhz, commercial 0 to 70 c, plcc 44 tsc251g2dxxx-24ce 32k maskrom 24 mhz, commercial 0 to 70 c, vqfp 44 tsc251g2dxxx-24ia 32k maskrom 24 mhz, industrial -40 to 85 c, pdil 40 tsc251g2dxxx-24ib 32k maskrom 24 mhz, industrial -40 to 85 c, plcc 44 at251g2dxxx-slsum 32k maskrom 24 mhz, industrial & green -40 to 85 c, plcc 44 at251g2dxxx-3csum 32k maskrom 24 mhz, industrial & green -40 to 85 c, pdil 40 at251g2dxxx-rltum 32k maskrom 24 mhz, industrial & green -40 to 85 c, vqfp 44 at251g2dxxx-slstm 32k maskrom 24 mhz, automotive & green -40 to 85 c, plcc 44 74 4135f?8051?11/06 at/tsc8x251g2d note: 1. xxx: means rom code, is cxxx in case of encrypted code. low voltage versions 2.7 to 5.5 v tsc251g2dxxx-l16cb 32k maskrom 16 mhz, commercial 0 to 70 c, plcc 44 TSC251G2DXXX-L16CE 32k maskrom 16 mhz, commercial 0 to 70 c, vqfp 44 at251g2dxxx-slsul 32k maskrom 16 mhz, industrial & green, plcc 44 at251g2dxxx-rltul 32k maskrom 16 mhz, industrial & green, vqfp 44 part number (1) rom description 75 4135f?8051?11/06 at/tsc8x251g2d at/tsc87251g2d otprom document revision history changes from 4135d to 4135e 1. added automotive qualification, and ordering information for rom product version. changes from 4135e to 4135f 1. absolute maximum ratings added for automotive product version. part number rom description high speed versions 4.5 to 5.5 v, commercial and industrial tsc87251g2d-16cb 32k otprom 16 mhz, commercial 0 to 70 c, plcc 44 tsc87251g2d-24cb 32k otprom 24 mhz, commercial 0 to 70 c, plcc 44 tsc87251g2d-24ced 32k otprom 24 mhz, commercial 0 to 70 c, vqfp 44 tsc87251g2d-24ia 32k otprom 24 mhz, industrial -40 to 85 c, pdil 40 tsc87251g2d-24ib 32k otprom 24 mhz, industrial -40 to 85 c, plcc 44 at87251g2d-slsum 32k otprom 24 mhz, industrial & green -40 to 85 c, plcc 44 at87251g2d-3csum 32k otprom 24 mhz, industrial & green -40 to 85 c, pdil 40 at87251g2d-rltum 32k otprom 24 mhz, industrial & green -40 to 85 c, vqfp 44 low voltage versions 2.7 to 5.5 v tsc87251g2d-l16cb 32k otprom 16 mhz, commercial 0 to 70 c, plcc 44 tsc87251g2d-l16ced 32k otprom 16 mhz, commercial 0 to 70 c, vqfp 44 at87251g2d-slsul 32k otprom 16 mhz, industrial & green, 0 to 70 c, plcc 44 at87251g2d-rltul 32k otprom 16 mhz, industrial & green, 0 to 70 c, vqfp 44 76 4135f?8051?11/06 at/tsc8x251g2d options (please consult atmel sales) ? rom code encryption ? tape & reel or dry pack ? known good dice ? extended temperature range: -55 c to +125 c product markings romless versions atmel customer part number part number yyww . lot number mask rom versions atmel part number yyww . lot number otp versions atmel part number yyww . lot number printed on recycled paper. 4135f?8051?11/06 ? atmel corporation 2006 . all rights reserved. atmel ? , logo and combinations thereof, and everywhere you are ? are the trademarks or regis- tered trademarks, of atmel corporation or its subsidiari es. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection with atmel products. no license, expr ess or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liabl e for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comple teness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically providedot- herwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not inten ded, authorized, or warranted for use as compo- nents in applications intended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature |
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